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Esp32sim is an MIT-licensed Rust emulator that runs firmware for four ESP32 models, including ESP32-S3, C3 and C6, in a browser through WebAssembly. Its project documentation reports that the emulated chips can boot real firmware images, while noting that some hardware comparisons are manual and CI does not run the full external decoder tests.
The open-source Esp32sim project has made a Rust-based emulator available in the browser, where it can run firmware for four ESP32 system-on-chips using WebAssembly. The project says the emulated devices boot their real mask ROM, second-stage bootloader and unmodified application images, offering developers a way to test some ESP32 projects without installing the emulator or connecting a physical board.
The project supports the classic dual-core ESP32 and the ESP32-S3, C3 and C6. Those chips cover both CPU architectures used in the lineup: Xtensa for the classic ESP32 and S3, and RISC-V for the C3 and C6. Esp32sim says each supported chip can proceed from ROM through the bootloader and FreeRTOS to an application, rather than relying on patched firmware or firmware stubs.
The browser build is available at the project’s GitHub Pages site, and the repository also provides command-line binaries and source code under the MIT license. The emulator includes shared models for components such as UART, GPIO, timers, SPI flash and cryptographic hardware. Board models add selected display, input, audio and other peripherals; for example, the S3 options include display-equipped boards, while the C3 is described as console-only. Capabilities vary by chip and board.
Esp32sim also models a virtual Wi-Fi access point and network functions including WPA2, DHCP, DNS and NAT to the host network, according to its documentation. The S3 supports a broader set of listed features than the C3 and C6. The project describes its speed as about 150–240 million instructions per second for the S3 using a block interpreter and AArch64 just-in-time compilation. The C3 and C6 use interpreters without a block cache or JIT, but the project says they run a hello-world example faster than real time.
A Browser Test Bench for ESP32
Running firmware in a browser could make early development and demonstration easier for people who do not have an ESP32 board at hand. It may also help users inspect how example firmware behaves before setting up a local toolchain. Since the emulator runs locally in the browser and the project says it requires no account or cloud service, it offers a different route from hosted development environments.
The practical value depends on how closely the modeled hardware matches the physical target and which peripherals a given project uses. Esp32sim’s support for selected boards, displays, networking and other devices goes beyond a simple CPU instruction simulator, but the project does not claim that every ESP32 feature or product is supported. Developers will still need to test hardware-dependent behavior on their actual boards before relying on an emulated result.
The multi-chip design also matters for people maintaining firmware across ESP32 variants. The repository says the C3 and C6 reuse many peripheral models from the S3 implementation, while each chip has its own CPU and chip-specific memory and interrupt components. That architecture gives the project a shared foundation, although it does not by itself establish how broadly real-world firmware will work.
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How Esp32sim Models the Chips
Esp32sim is built from separate Rust components for CPU emulation, SoC and peripheral models, boards, and the browser interface. A shared machine framework handles device timing, scheduling, consoles and scripts; chip-specific components supply the processor, memory map and interrupt routing. The web interface loads a WebAssembly module, while the same project can also be used from the command line.
The project’s documentation distinguishes between test types. It reports full-listing decoder checks of 977,000 instructions with no mismatches for the S3, 161,000 for the C3 and 126,000 for the C6, also with no mismatches. It says those checks came from earlier manual runs and are not part of the external full-listing tests run in continuous integration. CI instead runs checked-in sampled decoder corpora and emulator golden-output tests.
For hardware comparisons, the project reports console output matching 205 of 208 lines for the C3 and 203 of 204 for the C6. Its S3 comparison used JTAG traces after timing-loop resynchronization. The documentation says the hardware comparator normalizes window exceptions and resynchronizes delay loops, so the comparison is not uninterrupted, cycle-by-cycle agreement. These are project-reported results, not an independent evaluation.
“Each boots the real mask ROM, the real 2nd-stage bootloader and an unmodified application image.”
— Esp32sim project documentation
Limits of the Reported Tests
The supplied project material does not establish how many ESP32 firmware projects work in the emulator, or how behavior compares across a broad range of physical boards. It also does not provide an independent test of the project’s reported decoder counts, browser performance or hardware comparisons. Results from the listed examples should not be treated as proof that every application or peripheral combination will work.
Support is uneven across the four chips: the documentation labels the S3 implementation mature and the C3 and C6 implementations drafts. The project also lists some features as stand-ins or limited models, and the browser’s capabilities depend on the selected chip and board. It remains unclear from the supplied material how frequently those models will be updated or which unsupported devices are planned next.
Trying Firmware and Tracking Support
Readers can try the browser demo or build the command-line emulator from the project repository. The maintainers list example firmware for several chips, including a hello-world application, Wi-Fi station examples and demos using selected displays and radio features. Those examples provide a practical starting point, but users should check the board and peripheral support documented for their target.
The next useful milestones will be updates to the draft C3 and C6 implementations, broader documented firmware tests and clearer comparisons with physical hardware. The supplied material does not announce a release schedule or specific upcoming features. Until further results are published, the project’s current claims and test qualifications are best read as a description of an active emulator, not a guarantee of complete hardware equivalence.
Key Questions
Which ESP32 chips does Esp32sim support?
The project lists the classic ESP32, ESP32-S3, ESP32-C3 and ESP32-C6. The classic ESP32 and S3 use Xtensa processors; the C3 and C6 use RISC-V processors. The project describes the S3 implementation as mature and the C3 and C6 as drafts.
Can it run firmware in a browser?
Yes. The project provides a browser version built with WebAssembly. It also offers a Rust-based command-line option. Browser use does not require an account or a cloud service, according to the project.
Does Esp32sim support every ESP32 peripheral?
No such complete support is claimed in the supplied documentation. The emulator models many shared peripherals and selected board components, but support varies by chip and board. Users should check the repository’s device and board documentation for their firmware’s requirements.
How closely has it been tested against hardware?
The project reports console comparisons for the C3 and C6 and a JTAG trace comparison for the S3. It says some counts came from earlier manual runs, and the S3 comparison uses timing-loop resynchronization. The documentation cautions that this is not uninterrupted cycle-by-cycle agreement.
Source: hn
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